Semiconductor device failure analysis is a critical quality assurance process that identifies the root causes of device malfunctions through systematic electrical, physical, and material characterization. This technical guide covers the full scope of semiconductor failure inspection, including sample types, testing items, analytical methods, and industry applications. Whether you are dealing with integrated circuits, discrete devices, or power semiconductors, understanding failure analysis methodology is essential for improving product reliability and accelerating development cycles.
Technical Overview
Semiconductor device failure inspection, also known as failure analysis (FA), is a systematic engineering discipline designed to determine why a semiconductor device has ceased to function as specified or has exhibited degraded performance. The process integrates electrical characterization, non-destructive inspection, destructive physical analysis, and material science techniques to isolate the failure site, identify the failure mechanism, and determine the root cause. The findings then feed back into design, manufacturing, and process improvement activities.
Modern semiconductor devices are fabricated with feature sizes at the nanometer scale and packaged using increasingly complex structures such as flip-chip, wafer-level packaging, and 3D stacking with through-silicon vias (TSVs). As a result, failure analysis requires advanced instrumentation and disciplined workflows. A typical failure analysis flow follows the sequence of electrical fault isolation, non-destructive inspection, decapsulation or delayering, defect localization, and finally physical root-cause confirmation using high-resolution microscopy and analytical chemistry techniques.
Failure analysis is governed by internationally recognized standards, including JEDEC JEP149, JEDEC JESD22 series, IPC standards, IEC 60749, and ASTM test methods. Accredited third-party laboratories and in-house reliability teams use these standards to ensure consistent, reproducible, and legally defensible analytical results across the semiconductor supply chain.
Testing Samples
Integrated Circuits (ICs)
Digital, analog, and mixed-signal integrated circuits represent the largest category of failure analysis samples. These include microprocessors, microcontrollers, memory devices (DRAM, NAND flash, SRAM), application-specific integrated circuits (ASICs), system-on-chip (SoC) devices, and field-programmable gate arrays (FPGAs). Failures may occur at the die level, in the interconnect metallization, or within the package assembly.
Discrete Semiconductor Devices
Discrete devices such as diodes, rectifiers, Schottky barriers, bipolar junction transistors (BJTs), MOSFETs, and junction field-effect transistors (JFETs) are routinely submitted for failure inspection. Common failure modes include junction breakdown, thermal runaway, and bond wire fatigue.
Power Semiconductor Devices
Insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) MOSFETs, gallium nitride (GaN) HEMTs, and power diode modules are analyzed for failures related to high-voltage stress, switching losses, and thermal cycling in demanding applications such as electric vehicles, industrial drives, and renewable energy systems.
Optoelectronic and Sensor Devices
Light-emitting diodes (LEDs), laser diodes, photodetectors, CMOS image sensors, MEMS sensors, and RF devices form another important sample category. Their failure mechanisms often involve optical degradation, packaging-induced stress, and electromigration in high-frequency structures.
Components at Various Stages
Failure analysis samples may include bare wafers, packaged devices, board-level assemblies, and customer-returned units. Samples originating from reliability qualification testing, burn-in screening, production rejects, and field returns each require tailored analytical approaches.
Testing Items
Semiconductor device failure inspection encompasses a broad set of electrical, thermal, and structural testing items, including:
- Electrical parameter verification: continuity, leakage current, breakdown voltage, threshold voltage, and functional performance against datasheet specifications
- Open and short circuit detection across pins, bumps, and internal interconnects
- I-V curve tracing and curve comparison between failed units and known-good devices
- Thermal characterization using infrared thermography and thermal imaging to locate hot spots
- Die-level fault isolation using photon emission microscopy, thermal laser stimulation, and optical beam induced resistance change (OBIRCH)
- Scanning acoustic microscopy (SAM/CSAM) inspection for delamination, voids, and cracks in packaging layers
- X-ray radiography and X-ray computed tomography (CT) for wire bond integrity, solder joint quality, and internal structural anomalies
- Die and package surface inspection using optical microscopy and scanning electron microscopy (SEM)
- Cross-sectional analysis of dielectric layers, metallization, vias, and solder joints
- Material composition analysis using energy-dispersive X-ray spectroscopy (EDS/EDX), Auger electron spectroscopy (AES), secondary ion mass spectrometry (SIMS), and X-ray photoelectron spectroscopy (XPS)
- FIB (focused ion beam) circuit modification, micro-sectioning, and transmission electron microscopy (TEM) sample preparation
- Contamination and corrosion analysis, including ionic residue testing and moisture sensitivity assessment
Testing Methods
Non-Destructive Analysis
The first phase of any failure analysis workflow prioritizes non-destructive techniques that preserve evidence. External visual inspection under stereo and metallurgical microscopes identifies physical damage, corrosion, discoloration, and marking anomalies. X-ray inspection reveals internal defects such as broken bond wires, wire sweep, die attach voids, and solder bridging. Scanning acoustic microscopy detects subsurface delamination and popcorning damage in plastic packages that X-ray cannot resolve. Infrared thermography localizes abnormal heat generation during device operation.
Electrical Characterization and Fault Isolation
Comprehensive electrical testing confirms the failure signature and compares it against golden reference units. Curve tracing pinpoints abnormal junction behavior, leakage paths, and resistive opens. Advanced fault isolation techniques follow, including emission microscopy (EMMI), which detects photon emission from forward-biased junction defects and gate oxide breakdown sites, and laser-based stimulation methods such as OBIRCH and thermally induced voltage alteration (TIVA), which map resistance anomalies in metal interconnects. Capacitance-voltage measurement and charge pumping further characterize oxide and interface quality.
Destructive Physical Analysis
Once the failure site is localized, destructive sample preparation begins. Chemical decapsulation removes plastic molding compound to expose the die while preserving bond wires and electrical structures. Ceramic and metal package opening uses mechanical or plasma techniques. Delayering removes passivation, interlayer dielectric, and metal layers sequentially to expose buried defects. Parallel lapping and ion milling prepare cross-sections for SEM and TEM examination, which reveal intergranular corrosion, dielectric thinning, electromigration voids, and contact spiking at nanometer resolution.
Chemical and Material Analysis
Surface and bulk material characterization identifies contamination, wrong materials, and process-induced impurities. EDS mapping shows elemental distribution in solder joints and metallization. FTIR spectroscopy identifies organic contamination. Ion chromatography quantifies ionic residues that cause leakage and corrosion. SIMS and AES provide trace-level dopant and contamination profiling. These chemical techniques are essential for confirming root causes involving contamination, inadequate cleaning, or material substitution.
Reliability and Environmental Stress Testing
To verify failure mechanisms and reproduce field failures, laboratories apply accelerated stress tests in accordance with JESD22, IEC 60749, and AEC-Q100/Q101 guidelines, including:
- High temperature operating life (HTOL) and high temperature storage life (HTSL)
- Temperature humidity bias (THB, 85°C/85%RH) and highly accelerated stress testing (HAST)
- Temperature cycling (TC) and thermal shock (TS)
- Electrostatic discharge (ESD) testing per human body model (HBM), charged device model (CDM), and machine model (MM)
- Electrical overstress (EOS) verification and latch-up testing
Applications
Semiconductor failure inspection serves a wide range of industries and engineering scenarios:
- Automotive electronics: root cause analysis of failures in engine control units, ADAS modules, and powertrain inverters governed by AEC-Q100 and IATF-aligned quality systems
- Consumer electronics: resolution of field returns for smartphones, laptops, wearables, and home appliances to reduce warranty costs
- Industrial automation: diagnosis of failures in PLCs, motor drives, sensors, and programmable logic devices operating in harsh environments
- Telecommunications and data centers: analysis of high-speed transceivers, baseband processors, and power management ICs where uptime is critical
- Aerospace and defense: comprehensive failure investigation for radiation-hardened and high-reliability devices conforming to MIL-STD-883 methods
- Medical devices: failure analysis of implantable and diagnostic electronics where patient safety demands rigorous root cause determination
- Wafer fabrication and packaging: yield learning, process excursion investigation, and new product qualification support for semiconductor manufacturers
- Supply chain quality: independent verification of component authenticity, screening of counterfeit parts, and incoming lot acceptance testing
FAQ
What is the typical workflow of semiconductor device failure analysis?
A standard workflow begins with failure verification and visual inspection, followed by non-destructive techniques such as X-ray and scanning acoustic microscopy. Electrical characterization and fault isolation then localize the defect. Destructive analysis, including decapsulation and cross-sectioning, exposes the failure site for microscopic and chemical confirmation. The process concludes with a root cause determination report and corrective action recommendations.
How long does a failure analysis investigation take?
Simple failures confirmed by non-destructive methods may be resolved within a few working days. Complex cases requiring delayering, TEM analysis, or stress test reproduction can take several weeks. The timeline depends on failure complexity, sample condition, and the depth of root cause investigation required.
Why is non-destructive testing performed before destructive analysis?
Non-destructive techniques preserve the physical evidence of failure. Once a sample is decapsulated or cross-sectioned, certain information such as package-level delamination patterns or particle-induced damage cannot be recovered. Following a structured sequence maximizes the information extracted from each often irreplaceable failed unit.
What is the difference between a failure mode and a failure mechanism?
A failure mode is the observable manner in which a device fails, such as an electrical short or open circuit. A failure mechanism is the underlying physical or chemical cause, such as electromigration, gate oxide breakdown, or bond wire corrosion. Failure analysis aims to progress from the observed mode to the confirmed mechanism and ultimately to the root cause in design or manufacturing.
Can failure analysis be performed on a single failed unit?
Yes. Many investigations begin with a single field-return unit. However, having multiple failed samples and known-good reference devices significantly improves diagnostic confidence by enabling curve comparisons and distinguishing systematic defects from isolated anomalies.
Which standards govern semiconductor failure analysis?
Key references include the JEDEC JESD22 series and JEP149 for failure analysis guidelines, IEC 60749 for environmental and endurance testing, MIL-STD-883 for microelectronic device test methods, AEC-Q100 and AEC-Q101 for automotive-grade qualification, and applicable IPC standards for assembly and interconnect structures.